The present invention relates to the field of electronic circuits, and in particular, programmable phase shift circuitry.
Many electronic systems use a master clock signal to synchronize the operation of all the circuitry and integrated circuit. A fundamental concept in electronic design, synchronous operation is important to ensure that logic operations are being performed correctly. In a system, an integrated circuit may generate its own internal clock based on the master clock signal. For example, this integrated circuit may be a microprocessor, ASIC, PLD, FPGA, or memory. The internal clock is synchronized with the master clock. And in order to ensure proper operation, it is often important to reduce skew for the internal clock of the integrated circuit.
The integrated circuit may use an on-chip clock synchronization circuit such as a phase locked loop (PLL) or delay locked loop (DLL). The synchronization circuit locks or maintains a specific phase relationship between the master clock and the internal clock. When the system is started, it is desirable that the internal clock be locked to the master clock as rapidly as possible. Under some circumstances, such as when there is a wide frequency difference between the two clock, the locking time may be slow. This is because the locking time may be dependent on the slower of the two frequencies. A slower locking time is undesirable because it will take longer for the system to initialize before normal operation. Also, as the master clock varies, it will take longer for the clock synchronization circuit to track these variations.
Therefore, techniques and circuitry are needed to address this problem of clock synchronization circuitry with slow lock acquisition times. Further, it is desirable to provide programmable phase shift selection.
The invention provides a programmable phase shift feature for a phase locked loop (PLL) or delay locked loop (DLL) circuit. The phase shift may be adjusted with equal steps. Each step may be a fixed percentage of the clock period, and will be independent of supply voltage, temperature, and process parameters. Having an on-chip PLL or DLL is an important feature in programmable logic devices (PLDs). Users can use a PLL to improve circuit performance and generate clocks with different frequencies. The phase requirement for the output clock varies depending on the application. A very useful feature for users is the ability to tune the phase of the output clock, and for the result to be independent of process, temperature, and power supply.
In an embodiment, a voltage controlled oscillator (VCO) is implemented using a ring oscillator with approximately equal delay for each stage. Other circuit implementations for a VCO may also be used, including those well known to one of skill in the art. The delay is controlled by the voltage from charge pump The number of stages in the VCO is programmable. This programmability allows a wider frequency range for the VCO. As a higher frequency as specified, a fewer number of stages are needed.
In an embodiment, there are also two counters M and K. Both counter M and counter K are programmable frequency dividers. The M counter divides the VCO clock by a ratio M, and the K counter divides the VCO clock by a ratio K. The frequency of an output clock of the PLL will be given by Fout=Fin*M/K. Each counter has a asynchronous preset input (or clear input) connected to an asynchronous preset input 2412. The preset input is used to initialize the circuitry.
An input clock Fin and a feedback clock FFB are input into a phase detector circuit. FFB is generated by counter M and is the divided down clock generated by counter M. The output of the phase detector is input in the VCO, which generates a number of clock signals. One of these is selected by a multiplexer circuit to input a selected clock signal to counter M. Using the multiplexer to choose selected clock signal provides a fine adjustment feature for the phase shift provided by the circuitry. One of the clock outputs of the VCO is input to counter K. Counter K generates the output clock Fout.
In an embodiment, the invention is a phase-locked loop circuit including a voltage controlled oscillator providing a VCO clock output; a first counter having a first clock input connected to the VCO clock output; and a second counter having a second clock input connected to the VCO clock output, where the second counter generates an output clock of the phase-locked loop circuit.
Each counter may include a number of flip-flops; a number of counter logic blocks connected to the flip-flops; a number of first storage bits connected to the counter logic blocks, where the first storage bits are used to store a divider ratio for the first counter; and a number of second storage bits connected to the flip-flops, where the second storage bits are used to store an initial value for the first counter.
In another embodiment, the invention is a method of operating a phase-locked loop circuit by loading a first divider ratio in a first counter of the circuit; loading a second divider ratio in a second counter of the circuit loading a first initial value in the first counter; loading a second initial value in the second counter; and providing an output clock from the second counter having a phase difference from an input clock based on the first divider ratio, second divider ratio, first initial value, and second initial value.